Recently, Digital cameras and Camera phones are rapidly being developed and commercialized. Digital cameras and Camera phones generally sense light using semiconductor sensors, and the semiconductor sensors mainly used include a Complementary Metal-Oxide-Silicon (CMOS) image sensor and a Charge Coupled Device (CCD) image sensor.
A CMOS image sensor refers to a device for converting optical images into electrical signals using CMOS manufacturing technology and employs a switching method of providing a number of MOS transistors corresponding to the number of pixels and sequentially detecting outputs using the transistors. Currently, in contrast to the CCD image sensor widely used as an image sensor, the CMOS image sensor has advantages in that the driving method thereof is easy, various scanning methods can be implemented, it is possible to make products compact because signal processing circuits can be integrated into a single chip, manufacturing costs can be lowered because compatible CMOS technology is used, and power consumption can be greatly reduced.
FIG. 1 is a block diagram of a conventional CMOS image sensor. Referring to FIG. 1, the CMOS image sensor includes a pixel array 110, a row decoder 130, a Correlated Double Sampling (CDS) unit and Analog Digital Converter (ADC) (hereinafter referred to as a “CDS & ADC”) 150, and a column decoder 170.
In the pixel array 110, unit pixels, shown in FIG. 2, are arranged, a row decoder 130 for assigning row addresses is disposed along one side of the pixel array 110 around the pixel array 110, and a column decoder 170, to which the outputs of the pixels are connected, for assigning the column addresses of the pixels is disposed in a direction perpendicular to the row decoder 130.
The row decoder 130 is composed of a plurality of row decoder cells each having a plurality of gates. Each of the row decoder cells receives input signals through an address input line, a transfer signal input line, a selection signal input line, and a reset signal input line, and outputs output signals through a reset gate signal output unit for outputting a reset gate signal generated in response to a reset signal, which is entered through the reset signal input line, and an address signal, which is entered through the address signal input line, a selection gate signal output unit for outputting a selection gate signal generated in response to a selection signal, which is entered through the selection signal input line, and an address signal, which is entered through the address signal input line, and a transfer signal output line for outputting a transfer signal that is entered through the transfer signal input line.
In a detailed process of extracting data from the image sensor, a first row is selected by the row decoder 130, the respective pixel data of the first row selected by the column decoder 170 are extracted, and then the extracted pixel data are amplified. Thereafter, a second row is selected by the row decoder 130, the respective pixel data of the second row selected by the column decoder 170 are extracted, and then the extracted pixel data are amplified. In this manner, the data of overall pixels are extracted.
Meanwhile, the CDS & ADC unit 140 operates such that it converts analog data, which are extracted from the unit pixels, into digital data, and realizes high image quality through sampling.
FIG. 2 is a circuit diagram of a unit pixel having a 4-Transistor (4-T) structure. With reference to FIG. 2, the unit pixel is composed of one photo diode PD and four NMOS transistors. The four NMOS transistors are composed of a reset transistor Rx for resetting the potential of the photo diode in response to the reset gate signal, a transfer transistor Tx for transferring electrons, which are charged in the photo diode, to a floating diffusion region in response to the transfer signal, a drive transistor Dx for changing the output voltage of each unit pixel by changing the current of a source follower circuit according to variation in the electrode voltage of the floating diffusion region, and a select transistor Sx for outputting the output voltage of each unit pixel, which is generated according to variation in the voltage of the floating diffusion region, as analog output voltage in response to the selection gate signal.
The detailed operation of the unit pixel is described with reference to the operational timing diagram of FIG. 3. First, when a corresponding row is selected by a selection gate signal SG, the select transistor Sx is turned on, and the reset transistor Rx resets the voltage of a floating diffusion region by a reset gate signal RG. Thereafter, when light enters into the photo diode, electrons are generated. When the transfer transistor Tx is turned on by a transfer gate signal TG, charges based on the accumulation of the electrons generated at the photo diode are transferred to the floating diffusion region, and the drive transistor Dx changes the output voltage of the unit pixel in proportion to the amount of charge in the floating diffusion region.
In FIG. 3, level ‘a’ is the initial voltage level of an output node after the corresponding row has been selected by the selection gate signal SG, level ‘b’ is the voltage level of an output node after the reset has been performed by the reset gate signal RG, and level ‘c’ is a voltage level after diffusion into the floating diffusion region has been performed by the transfer gate signal. In this case, the difference between the voltage levels ‘b’ and ‘c’ of the output node is output as an actual image data signal.
FIG. 4 is a general circuit diagram of a conventional row decoder. Referring FIG. 4, the reset gate signal RGi, transfer gate signal TGi, and selection gate signal SGi of an i-th row, the reset gate signal RGi+1, transfer gate signal TGi+1, and selection gate signal SGi+1 of an i+1-th row, and the reset gate signal RGi+2, transfer gate signal TGi+2, and selection gate signal SGi+2 of an i+2-th row are generated by the combination of row addresses Ai, Ai+1, and Ai+2 and a transfer signal T, and a selection signal S and a reset signal R.
In this case, a timing diagram shown in FIG. 5 is used because the CMOS image sensor selects respective rows using shift registers and then activates unit pixels.
FIG. 5 is a timing diagram when the conventional image sensor outputs respective pixel data at respective unit pixels.
Referring to FIG. 5, the CMOS image sensor selects a first row using a selection gate signal SG1, performs reset using a reset gate signal RG1, and then measures the voltage (reset value) of the floating diffusion region after the reset. Thereafter, the CMOS image sensor allows the charges, which have been accumulated in the photo diode, to be transferred to the floating diffusion region by a transfer gate signal TG1 and then measures the voltage (pixel data) of the floating diffusion region again. Thereafter, the CMOS image sensor selects a second row using a selection gate signal SG2 and repeats the above-described process.
In the above-described method of outputting image data, the time point when the first row receives light and the time point when the n-th row receives light are different when n (where n is a natural number) rows exist. In this case, a problem exists in that a moving image can be distorted when the CMOS image sensor photographs the image.